Instruction-set interface
Define the operations, registers and memory model exposed to software independently of one microarchitecture.
Side 235Side Studies / Research
Subject
Computer Architecture
Purpose
Computing hardware studied through instruction sets, processors, memory hierarchies, parallelism and the trade-offs connecting software to physical execution.
Structure
05 movesSystem mapV0
Components → constraints → flows → control → failure
Follow an instruction through the machine.
Computer architecture explains performance by connecting abstractions visible to software with pipelines, caches, memory and parallel execution underneath.
Datapath & control
Trace instruction fetch, decode, execution and retirement through processor structures.
Pipelining & speculation
Increase throughput by overlapping work while managing hazards, branches and recovery from wrong predictions.
Memory hierarchy
Use caches and locality to bridge the speed gap between processors and larger memory systems.
Parallelism & performance
Study multicore, vector and accelerator architectures while separating peak throughput from realized application performance.
Keep the boundaries visible.
ISA ≠ microarchitecture
clock speed ≠ performance
cache hit rate ≠ application speed
Questions that organize the Side.
Which bottleneck dominates a workload: compute, latency, bandwidth or synchronization?
How does speculation trade efficiency for complexity and energy?
When does hardware specialization justify reduced generality?
What should carry weight here?
Benchmark representative workloads, report energy and memory behavior, and separate synthetic microbenchmarks from end-to-end performance.